Previously explained was a simple SR Latch that was holding its last states on specific input. Often there is a need to enable or disable a latch. To accomplish the same we need to have an extra input pin called clock for enabling or disabling the latch. When disabled, the previous states remain unchanged. Circuit that uses this type of mechanism are called gated latches. In this case the circuit is called Gated SR Latch.
This latch is active high, that is when clock signal goes high the Gates SR Latch behaves as a normal SR Latch. And when the clock signal goes low, whatever the logic at inputs maybe, the output will remain the same unless and until the clock signal goes high again.
The characteristic table is given below. Many authors use the term characteristic table rather than truth table - this is because truth table is usually linked with the circuits whose output(s) solely depends upon the input(s) only which is not the case here. The table below is same as that of SR Latch except that it is controlled using clock signal.