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A Memory Element using NOR Gate - SR Latch


A memory element is referred to as a storage element. A basic memory element can formed using NAND or NOR gate. The above arrangement of NOR gate is a basic memory element that can withhold a logic. The arrangement below is a modified version which is also known as SR Latch. 

Summarization of mentioned characteristic table for above SR latch is given below :
  1. When Q=0, Q'=1 and when Q=1,Q'=0 under normal conditions
  2. When R=0 and S=1, the latch is set into "S E T" state i-e Q=1 and Q'=0
  3. When R=1 and S=0, the latch is set into "R E S E T" state i-e Q=0 and Q'=1
  4. When both R and S equals low logic, the SR latch holds is previous states
  5. The last possibility of R=S=1 gives us the illegal (unpredictable|) value. Some authors say that Q=Q'=0 in this state.
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Posted by Muhammad Ahmed on 09:39. Filed under , , . You can follow any responses to this entry through the RSS 2.0. Feel free to leave a response

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